EE 5323 VLSI Design I : Slides and Handouts

 

NOTE: Permission to use these slides for educational purposes is granted, provided that all copyright notices are preserved.

  Topic Slides (pdf, 4 slides per page) Notes
1 Introduction 01_Intro.pdf  
2 MOS Lect_02_MOS1.pdf
Rabaey's slides here		 2008_09_08
2008/09/10
 
2008/09/12
 
3 Inverter (Ch 5) CMOS Inverter 
Slides
Rabaey's slides
2008/09/15
2008/09/17
2008/09/19

static: cumm
day
transient
4 Power / Delay Slides: Lect_04_Inverter2.pdf
2008/09/22 inp rise time, power (sc, dyn)
2008/09/24 PDP metric, Inv chain sizing
5 Vt, Short Ch Slides: Lect_05_MOS2.pdf
2008/09/29 Body bias, Vt
2008/10/01 MOS capacitance
2008/10/03 Leakage
6 Wires Slides: Lect_06_Wires
2008/10/08 Wire scaling, Elmore Delay
2008/10/10 gate resistor + wire
7 Combinational circuits Slides: rabaey's chap 6 slides
2008/10/10 CMOS gates (NAND, NOR)
2008/10/13 NAND VTC, timing
2008/10/15 2008_10_15_speedupCmos
2008_10_15_layoutTeq
2008/10/17 Logical Effort - part 1
2008/10/20 Logical Effort - Parts 1& 2
2008/10/22 Logical effort example (last two slides), power (dyn+glitch)
2008/10/24 Glitch (last page new),
Logic classes
2008/10/31 Logic classes (last 4 slides new)
2008/11/3 Logic classes (slides 9-15 new)
2008/11/05 Logic classes (slides 16-20 new)
8 Adders

Adders.ppt

  
9 Dynamic Logic domino.ppt
2008/11/14 Dynamic logic
2008/11/15 Taped outside class: watch / download .swf flash file (28MB)
2008/11/17 Solution to midterm probs 1, & 3, 
Domino timing
2008/11/19 skewed CMOS (only the last pagenew)
10 Sequential Logic  
2008/11/19 Latch
2008/11/21 Latch, SRAM (page 3-7 new)
2008/11/24 latch, Flip-Flop (pages 8-10 new)
2008/11/26 FF timing, dyn reg
VIDEO: watch (or download it)
2008/12/01 Stacking effect, dual-Vt FF (Slides 11-13)
2008/12/03 dual-edge registers (slides 14-18)
2008/12/05 timing
2008/12/10 timing, schmitt, vco
watch the extra video (or download)