Publications

 

Book Chapters

  • Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "Synthesizing combinational logic to generate probabilities: theories and algorithms," in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati editors, Springer Publishing, 2011.
  • Kia Bazargan, "Chapter 10.2: FPGA Technology Mapping, Placement, and Routing", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press
  • Sachin Sapatnekar, Kia Bazargan, "Chapter 10.4: 3D Design", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press.

 

    Journal Papers

    • M. H. Najafi, D. J. Lilja, M. Riedel, and K. Bazargan, "Low Cost Sorting Network Circuits using Unary Processing", TVLSI - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 8, pp. 1063-8210, 2018.
    • M. H. Najafi, Shiva Jamali-Zavareh, D. J. Lilja, M. D. Riedel, K. Bazargan, and R. Harjani, "An Overview of Time-based Computing with Stochastic Constructs," in IEEE Micro, 2017.
    • M. H. Najafi, D. J. Lilja, M. D. Riedel and K. Bazargan, "Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits," in IEEE Transactions on Computers, vol. 66, no. 10, pp. 1734-1746, Oct. 1 2017.[Selected as IEEE Transaction on Computers' Feature Paper of the Month]
    • M. Hassan Najafi, P. Li, D. J. Lilja, W. Qian, K. Bazargan, M. Riedel, "A Reconfigurable Architecture with Sequential Logic-based Stochastic Computing," ACM Journal on Emerging Technologies in Computing Systems, Vol. 3, No. 4, 2017.
    • M. Hassan Najafi, S Jamali-Zavareh, D. J. Lilja, M. Riedel, K. Bazargan, and R. Harjani, "Time-Encoded Values for Highly Efficient Stochastic Circuits," IEEE Transaction on Very Large Scale Integration Systems, Vol. 25, No 5, 2017.
    • Zhiheng Wang, Ryan Goh, Kia Bazargan, Arnd Scheel, and Naman Saraf, "Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map" , in IEEE Transactions on VLSI (TVLSI), 2016.

     

    Conference Papers

    • Sayed Abdolrasoul Faraji, M. Hassan Najafi, Bingzhe Li, Kia Bazargan and David Lilja, "Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing", DATE, 2019.
    • Sayed Abdolrasoul Faraji, and Kia Bazargan, "Hybrid Binary-Unary Hardware Accelerators", Asia and South Pacific Design Automation Conference (ASP-DAC), 2019.
    • M. Hassan Najafi, Sayed Abdolrasoul Faraji, Bingzhe Li, David Lilja and Kia Bazargan, "Using Resolution Splitting to Enhance Performance of Deterministic Bit-Stream Computing", 27th International Workshop on Logic & Synthesis (IWLS), 2018.
    • David Orser, Kia Bazargan, and John Sartori, "Harnessing State of the Art Internet of Things Labs to Motivate First-Year Electrical and Computer Engineering Students", American Society for Engineering Education (ASEE) Annual Conference and Exposition, 2018.
    • Soheil Mohajer, Zhiheng Wang, and Kia Bazargan, "Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data", International Symposium on Field Programmable Gate Arrays (FPGA), pp. 77-86, 2018.
    • Zhiheng wang, Soheil Mohajer, and Kia Bazargan, "Low Latency Parallel Implementation of Traditionally-Called Stochastic Circuits using Deterministic Shuffling Networks," Asia and South Pacific Design Automation Conference (ASP-DAC), 2018.
    • M. Hassan Najafi, D. J. Lilja, M. Riedel, and K. Bazargan, "Power and Area Efficient Sorting Networks using Unary Processing," (ICCD), 2017. [Selected among the top ranked ICCD papers to be published in the IEEE TETC]
    • M. Hassan Najafi, S Jamali-Zavareh, D. J. Lilja, M. Riedel, K. Bazargan, and R. Harjani, "Time-Encoded Values for Highly Efficient Stochastic Circuits," IEEE International Symposium of Circuits and Systems (ISCAS), Baltimore, MD, USA, 2017.
    • M. Hassan Najafi, D. J. Lilja, M. Riedel and K. Bazargan, "Polysynchronous stochastic circuits," 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 492-498, 2016.
    • Naman Saraf and Kia Bazargan, "Polynomial Arithmetic Using Sequential Stochastic Logic", Great Lakes Symposium on VLSI (GLSVLSI), 2016. [nominated for the best paper award].
    • Naman Saraf and Kia Bazargan, "Improving Linear Feedback Shift Registers Using Similarity Transformations", Dallas Circuits and Systems Conference (DCAS), 2015.
    • Zhiheng Wang, Naman Saraf, Kia Bazargan and Arnd Scheel, "Randomness Meets Feedback: Stochastic Implementation of Logistic Map Dynamical System", Design Automation Conference (DAC), 2015.
    • Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmailzadeh and Kia Bazargan, "AXILOG: Language Support for Approximate Hardware Design", Design, Automation and Test in Europe (DATE), 2015.
    • Naman Saraf, Kia Bazargan, David Lilja and Marc Riedel, "IIR Filters Using Stochastic Arithmetic", Design, Automation and Test in Europe (DATE), 2014.
    • Yanzi Zhu, Peiran Suo and Kia Bazargan, "Binary Stochastic Implementation of Digital Logic", International Symposium on Field-Programmable Gate Arrays (FPGA), 2014.
    • Naman Saraf, and Kia Bazargan, "Sequential Logic To Transform Probabilities", International Conference on Computer-Aided Design (ICCAD), 2013.
    • Naman Saraf, and Kia Bazargan, "Design of Sequential Logic to Generate Probabilities", International Workshop on Logic and Synthesis (IWLS), 2013.
    • Naman Saraf, Kia Bazargan, David Lilja, and Marc Riedel, "Stochastic Functions Using Sequential Logic", International Conference on Computer Design (ICCD), 2013.
    • Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan and Marc Riedel, "The Synthesis of Complex Arithmetic Computation on Stochastic Bit Streams Using Sequential Logic", International Conference on Computer-Aided Design (ICCAD), 2012.
    • Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, and Marc D. Riedel, "An Efficient Implementation of Numerical Integration Using Logical Computation on Stochastic Bit Streams", International Conference on Computer-Aided Design (ICCAD), 2012.
    • Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, and Marc Riedel, "Using Two-Dimensional Finite State Machine for Stochastic Computation", IWLS, 2012.
    • Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "The Synthesis of Linear Finite State Machine-Based Stochastic Computational Elements", Asia and South Pacific Design Automation Conference (ASP-DAC), 2012.
    • Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan and Marc D. Riedel, "Case Studies of Logical Computation on Stochastic Bit Streams," in Lecture Notes in Computer Science, editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen, Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS) workshop, Springer Publishing, 2012.
    • Pongstorn Maidee and Kia Bazargan, "A Fast SPFD-based Rewiring Technique", Asia South-Pacific Design Automation Conference (ASPDAC), 2010.
    • Weikang Qian, Marc Riedel, Kia Bazargan, and David Lilja, "The Synthesis of Combinational Logic to Generate Probabilities", International Conference on Computer-Aided Design (ICCAD), pp. 367-374, San Jose, 2009.(Slides)(Nominated for the Best Paper Award)
    • Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "A Reconfigurable Stochastic Architecture for Highly Reliable Computing", Great Lakes Symposium (GLSVLSI), 2009. (Slides)
    • Hamid Safizadeh, Mohammad Tahghighi, Ehsan Ardestani, Gholamhossein Tavassoli, and Kia Bazargan, "Using Randomization to Cope with Circuit Uncertainty", Design Automation & Test in Europe (DATE), 2009.
    • Satish Sivaswamy, Kia Bazargan, and Marc Riedel, "Estimation and Optimization of Reliability of Noisy Digital Circuits", International Symposium on Quality Electronic Design (ISQED), 2009.
    • Hushrav Mogal, and Kia Bazargan, "Thermal-Aware Floorplanning for Task Migration Enabled Active Sub-threshold Leakage Reduction", International Conference on Computer-Aided Design (ICCAD), 2008.
    • Pongstorn Maidee, Nagib Hakim and Kia Bazargan, "FPGA Family Composition and Effects of Specialized Blocks", International Conference on Field Programmable Logic and Applications (FPL), 2008.
    • Hushrav Mogal, Haifeng Qian, Sachin Sapatnekar and Kia Bazargan, "Clustering Based Pruning for Statistical Criticality Computation under Process Variations", International Conference on Computer-Aided Design (ICCAD), 2007.
    • Pongstorn Maidee and Kia Bazargan, "A Generalized and Unified SPFD-based Rewiring Technique", 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.
    • Satish Sivaswamy and Kia Bazargan, "Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs", 17th International Conference on Field Programmable Logic and Applications (FPL), 2007.
    • Satish Sivaswamy and Kia Bazargan, "Variation-Aware Routing for FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2007.
    • Hushrav Mogal and Kia Bazargan, "Microarchitecture Floorplanning for Sub-threshold Leakage Reduction", Design and Test in Europe (DATE), 2007.
    • Pongstorn Maidee and Kia Bazargan, "Defect-tolerant FPGA Architecture Exploration" , 16th International Conference on Field Programmable Logic and Applications (FPL), 2006.
    • Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), pp. 21-29, 2005.
    • C. Ababei, H. Mogal, and Kia Bazargan, "3D FPGAs: Placement, Routing and Architecture Evaluation", International Symposium on Field Programmable Gate Arrays (FPGA), (poster), 2005.
    • C. Ababei, H. Mogal, and Kia Bazargan, "Three-dimensional Place and Route for FPGAs", Asia South-Pacific Design Automation Conference (ASPDAC), pp. 773 - 778, 2005.
    • C. Ababei, and Kia Bazargan, "Exploring Potential Benefits of 3D FPGA Integration", Field-Programmable Logic and its Applications (FPL), 2004.
    • Y. Chen, K. Ranganathan, V. V. Pai, D. Lilja and Kia Bazargan, "Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory", Asia-Pacific Computer Systems Architecture Conference (ACSAC), 2004.
    • C. Ababei and Kia Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics", Reconfigurable Architectures Workshop (RAW), p., 2004.
    • W. Choi and Kia Bazargan, "Incremental Placement for Timing Optimization", International Conference on Computer-Aided Design (ICCAD), p., 2003.
    • C. Ababei and Kia Bazargan, "Placement Method Targeting Predictability, Robustness and Performance", International Conference on Computer-Aided Design (ICCAD), 2003.
    • P. Maidee, C. Ababei and Kia Bazargan, "Fast Timing-driven Partitioning-based Placement for Island Style FPGAs", Design Automation Conference (DAC), pp. 598-603, 2003. (Slides (zipped ppt)) (Nominated for the best paper award)
    • K. Bhasyam and Kia Bazargan, "HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming", Euromirco Symposium on Digital Systems Design, 2003.
    • V.K. Marreddy, S. Noorbaloochi and and Kia Bazargan, "Linear Placement for Static / Dynamic Reconfiguration in JBits", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 2003.
    • W. Choi and Kia Bazargan, "Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration", Design Automation and Test in Europe (DATE), 2003.
    • C. Aabei and Kia Bazargan, "Timing Minimization by Statistical Timing hMetis-based Partitioning", VLSI Design, pp. 58-63, 2003.
    • C. Aabei, N. Selva, Kia Bazargan and G. Karypis, "Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization", International Conference on Computer-Aided Design (ICCAD), pp. 181-185, 2002.
    • Jinghuan Chen, Jaekyun Moon, and Kia Bazargan, "A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator", Design Automation Conference (DAC), pp. 349-354, 2002.(Slides (zipped ppt)) (Nominated for the best paper award)
    • C. Ababei and Kia Bazargan, "Statistical Timing Driven Partitioning for VLSI Circuits", Design Automation and Test in Europe (DATE), pp. 1109, 2002.
    • Kia Bazargan, S. Ogrenci and M. Sarrafzadeh, "Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures", Design Automation Conference (DAC), pp. 635-640 , 2001. (Nominated for the best paper award)
    • S. Ogrenci, Kia Bazargan and M. Sarrafzadeh, "Image analysis and partitioning for FPGA implementation of image restoration", in Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 346-355, 2000.
    • Kia Bazargan and M. Sarrafzadeh, "Fast Scheduling and Placement Methods for C to Hardware/Software Compilation", SPIE International Symposium on Information Technologies, Vol. 4212, November 2000. (Slides)
    • A. Ranjan, Kia Bazargan and M. Sarrafzadeh, "Fast Hierarchical Floorplanning with Congestion and Timing Control", IEEE International Conference on Computer Design (ICCD), pp. 357-362, September 2000. (Slides)
    • Kia Bazargan, R. Kastner, S. Ogrenci and M. Sarrafzadeh, "A C to Hardware/Software Compiler", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 331-332, 2000.
    • Kia Bazargan, A. Ranjan and M. Sarrafzadeh, "Fast and Accurate Estimation of Floorplans in Logic/High-level Synthesis", Great Lakes Symposium on VLSI (GLSV), pp. 95-100, March 2000.
    • R. Kastner, Kia Bazargan and M. Sarrafzadeh, "Physical Design for Reconfigurable Computing Systems using Firm Templates", Workshop on Reconfigurable Computing (WoRC), pp. 19-26, 1999.
    • A. Ranjan, Kia Bazargan and M. Sarrafzadeh, "Floorplanner 1000 Times Faster: A Good Predictor and Constructor", in System-Level Interconnection Prediction (SLIP), pp. 115-120, 1999.
    • Kia Bazargan, R. Kastner and M. Sarrafzadeh, "3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems", 10th IEEE International Workshop on Rapid System Prototyping (RSP' 99), pp. 38-43, 1999.
    • Kia Bazargan and M. Sarrafzadeh, "Fast Online Placement for Reconfigurable Computing Systems", IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), pp. 300-302, 1999.
    • Kia Bazargan, S. Kim and M. Sarrafzadeh, "Nostradamus: A Floorplanner of Uncertain Designs", International Symposium on Physical Design (ISPD), pp. 18-23, 1998.