- Final project, Phase 1 due 12/1, Phase 2 due 12/12
- HW#5: Sequentail logic. NOT REQUIRED.
- HW#5: Dynamic gates. Due 11-26-08.
- HW#4: XOR layout. Due 10-27-08.
- HW#3: Complex static CMOS gates. Due 10-20-08.
- HW#2: Device and CMOS inverter. Due 10-13-08.
- HW#1: Inverter gate layout and simulation. Due 09-29-08.
Homework Policies
Refer to "Policies" section of the course page for homework policies.