Terms and Conditions (adapted from VPR's terms)

By downloading the tools linked from this page, you agree to:
1. All the software programs linked from this page are copyright Kia Bazargan, students whose names appear on the papers published on the tools, and the University of Minnesota.
2. Only non-commercial, not-for-profit use of this software is permitted. No part of this software may be incorporated into a commercial product without the written consent of the authors (Kia Bazargan and his students involved in developing the code). Similarly, use of this software to assist in the development of new commercial products is prohibited, unless the written consent of the authors is obtained.
3. This software is provided "as is" with no warranties or guarantees of support.
4. All users who download the tools agree not to redistribute their copy of the software to other persons.
5. You may modify or use the source code for other non-commercial, not-for-profit research endeavors, provided that all copyright attribution on the source code is retained, and the original or modified source code is not redistributed, in whole or in part, or included in or with any commercial product, except by written agreement with the authors, and full and complete attribution for use of the code is given in any resulting publications.
6. Subject to these conditions, all the tools linked from this page are provided free of charge to all interested parties.


Available Tools

The following tools are currently available for download:


HARP: HArd-wired Routing Pattern FPGA placement and routing

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. However, providing such great flexibility comes at a high cost in terms of area, delay and power. HARP is a new routing architecture that has a mixture of hardwired and traditional flexible switches to improve the area, power and performance.

  • Acknowledgements
    • This work is supported in part by NSF under contract CAREER CCF-0347891. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
    • HARP is implemented on top of  Power Model to enable power consumption estimation of the HARP architectures.
  • Related papers (check Kia's publications page for more): 
    • Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2005.
  • Read more about HARP
  • Download HARP (Make sure that you read and agree to the terms outlined above before you download)


[3D-ADOpt] TPR: Three dimensional Place and Route for FPGAs

Three dimensional IC fabrication where multiple active device layers are stacked is becoming a viable process. CAD tools are needed to map circuits on such architectures. We have extended both our PPFF (partitioning-based) and the VPR  tools to perofrm placement and routing for 3D ICs.


PPFF: Partitioning-based Placement For FPGAs

PPFF is a partitioning-based placement tool for island-based FPGAs. It is built on top of the VPR code. Use of a partitioning engine results in 3-4x speedup compared to VPR (which uses Simulated Annealing), while generating placements that are as good as VPR's. The high quality of the placement is the result of an "alignment" heuristic combined with a routing resource budgeting during partitioning.