Terms and Conditions (adapted from VPR's terms)
Available Tools
The following tools are currently available for download:
- HARP: HArd-wired Routing Pattern FPGA placement and routing.
- TPR: Three dimensional Place and Route for FPGAs.
- PPFF: Partitioning-based Placement For FPGAs.
HARP: HArd-wired Routing Pattern FPGA placement and routing
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. However, providing such great flexibility comes at a high cost in terms of area, delay and power. HARP is a new routing architecture that has a mixture of hardwired and traditional flexible switches to improve the area, power and performance.
- Acknowledgements
- This work is supported in part by NSF under contract CAREER CCF-0347891. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
- HARP is implemented on top of Power Model to enable power consumption estimation of the HARP architectures.
- Related papers (check Kia's publications page for more):
- Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2005.
- Read more about HARP
- Download HARP (Make sure that you read and agree to the terms outlined above before you download)
[3D-ADOpt] TPR: Three dimensional Place and Route for FPGAs
Three dimensional IC fabrication where multiple active device layers are stacked is becoming a viable process. CAD tools are needed to map circuits on such architectures. We have extended both our PPFF (partitioning-based) and the VPR tools to perofrm placement and routing for 3D ICs.
- Acknowledgement: this work is supported in part by a DARPA grant as part of our 3D-ADOpt project.
- Related papers (check Kia's publications page for more):
- C. Ababei, H. Mogal, and K. Bazargan, "Three-dimensional Place and Route for FPGAs", Asia South-Pacific Design Automation Conference (ASPDAC), 2005.
- C. Ababei, and K. Bazargan, "Exploring Potential Benefits of 3D FPGA Integration", Field-Programmable Logic and its Applications (FPL), 2004.
- Read more about TPR
- Download TPR (Make sure that you read and agree to the terms outlined above before you download)
- Download SA-TPR (Make sure that you read and agree to the terms outlined above before you download)
PPFF: Partitioning-based Placement For FPGAs
PPFF is a partitioning-based placement tool for island-based FPGAs. It is built on top of the VPR code. Use of a partitioning engine results in 3-4x speedup compared to VPR (which uses Simulated Annealing), while generating placements that are as good as VPR's. The high quality of the placement is the result of an "alignment" heuristic combined with a routing resource budgeting during partitioning.
- Related papers (check Kia's publications page for more):
- P. Maidee, C. Ababei and K. Bazargan, "Fast Timing-driven Partitioning-based Placement for Island Style FPGAs", Design Automation Conference (DAC), pp. 598-603, 2003.
- Read more about PPFF
- Download PPFF (Make sure that you read and agree to the terms outlined above before you download)